1. Field of the Invention
The present invention relates to a direct memory controller (DMAC) for transferring data between a memory and peripheral device.
2. Description of the Related Art
Information processing apparatuses including a personal computer and workstation generally use a DMA transfer method for transferring data between a main memory and peripheral device. In the DMA transfer method, a request for data transfer to a DMAC from CPU (Central Processing Unit) means that the DMAC controls the data transfer between a main memory and peripheral device. Accordingly the CPU does not need to concern the data transfer and is able to perform other processes.
FIG. 6 is a timing chart showing a flow of an operation example by CPU and DMA in a conventional DMA transfer apparatus. The direction indicated by the arrow in the drawing refers to a time axis of the processes. Further, “DMA transfer setting” and “interruption process” are performed by CPU and “DMA transfer setting” is performed by DMAC.
As shown in the timing chart of FIG. 6, before starting a DMA transfer, a memory start address and data transfer count are configured. After completing the DMA transfer corresponding to the content configured, a memory start and data transfer count for a next DMA transfer are configured. In such DMA transfer apparatus, the next DMA transfer setting cannot be configured until the data currently being transferred is completed, thereby generating problems that the CPU is overloaded and the processes cannot be carried out at high-speed.
A method is suggested for preventing configurations for the abovementioned DMA transfer from being concentrated on particular time so as to relieve the load on the CPU (see Japanese Unexamined Patent Application Publication No. 8-278938 and Japanese Unexamined Patent Application Publication No. 2000-20455).
According to the method, a DMAC includes two setting registers so that during a DMA transfer according to a DMA transfer setting stored in a first setting register, setting for a second DMA transfer can be configured to another setting register.
A process flow of the configuration of a DMA transfer setting using two registers is considered hereinafter with reference to FIG. 7. As with FIG. 6, FIG. 7 is a timing chart showing an operation flow of CPU and DMAC, where the direction indicated by the arrow in the drawing indicates the time axis of the process. Further, “DMA transfer setting” and “interruption process” are performed by CPU and “DMA transfer setting” is performed by DMAC.
As shown in the drawing, when a DMA transfer request for data B is generated during a DMA transfer for data B, a DMA transfer setting for the data B is stored to the second setting register. Further, after completing the DMA transfer for the data A, a DMA transfer setting for the data B that is stored in the second setting register is overwritten to the first setting register, and a DMA transfer for the data B is carried out. Likewise, when a DMA transfer request for data C is generated while transferring the data B, a DMA transfer setting for the data C is stored in the second setting register so as to carry out the DMA transfer for the data C after completing the DMA transfer for the data B.
However, if a DMA transfer request for data X is generated during the DMA transfer for the data C and also the DMA transfer setting for data D is already stored to the second setting register, a DMA transfer setting for the new data X may be overwritten before starting the DMA transfer for the data D in the second setting register. As a result, it has now been discovered that the DMA transfer for the data X is carried out but not the DMA transfer for the data D.